Senior ASIC Verification Engineer

SENIOR ASIC VERIFICATION ENGINEER

We are seeking a motivated, detail-oriented engineer with:

• Strong analytical and problem-solving skills
• A proactive mindset and eagerness to learn
• A solid foundation in ASIC verification methodologies4
• The drive to grow and contribute to high-impact projects

At Capgemini, we foster a collaborative and supportive environment where innovation thrives. You will have the opportunity to:

• Work on exciting, industry-leading projects
• Expand your skills with continuous learning
• Make meaningful contributions from day one

If you're ready to grow your expertise and make a difference in a fast-paced, forward-thinking team, we encourage you to apply!

KEY RESPONSIBILITIES

• Proficiency in UVM, SystemVerilog, and C/C++
• Experience with SystemVerilog simulators and waveform debuggers
• Hands-on experience in SystemVerilog test bench development, including:
• Strong debugging and analytical skills, with the ability to identify issues in architecture, functionality, and performance
• Stimulus generation
• Checkers, assertions, scoreboarding
• Transactors/BFMs
• Functional coverage and cover points

ACADEMIC CREDENTIALS

• BSEE or equivalent. MSEE preferred