Middle RTL Engineer (Ukraine)

Job Description

Implement Design Microarchitecture at RTL level for high-performance blocks based on Functional Specification from Senior Engineers and Architects Perform RTL Debugging, ensuring design correctness and efficiency Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks Collaborate with verification, physical design, and architecture teams (Bonus) Contribute to Front-End Synthesis and optimization (Nice to have) Experience working on SoC-level integration and design (Nice to have) Apply Power Optimization Techniques for energy-efficient designs

What You Bring:

3+ years of hands-on experience in digital design

Willingness to constantly learn from senior colleagues Strong knowledge of Verilog and/or VHDL for synthesis Familiarity with SystemVerilog is a plus Experience with tools like Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler is a plus Proven experience in RTL design, uArch development, and functional specs Basic understanding of linting tools, CDC methodologies, and debugging flows Familiarity with synthesis tools and SoC design is a strong plus Bachelor's degree in EE, ECE, CE, CS, or a related field required MS or PhD highly desired

Good communication and collaboration skills

What you will have working here

• We care about all our employees and want them to feel as comfortable as possible. That's why we offer health insurance from the first days, regardless of the probationary period.
• The Gift from the Company - Christmas holidays from December 25 to December 31.

      • Cooperation with Superhumans center and Veteran HUB. Capgemini Engineering has supported the launch of psychological rehabilitation department of Superhumans. Our team also donated over UAH 500 000 prosthetics for three Ukrainian defenders. Currently, we support psychological counseling provided by the Veteran Hub, and we have implemented an internal policy making the company friendly to military and veterans with the assistance of the Hub.