Analog Designer

Job Description

We are seeking a Lead Analog Circuit Designer with hands-on experience in planar CMOS technologies. The ideal candidate selects and tailors circuit topologies to the target application (consumer, automotive, aerospace, industrial), designs for robust performance under parasitics and variability, and ensures reliability across process, voltage, and temperature (PVT) with consideration of long-term aging mechanisms (BTI/HCI).
Key Responsibilities
Translate system requirements into block-level analog specifications; choose appropriate topologies per application class (e.g., low-power consumer, high-reliability automotive, mission/temperature-critical aerospace).
Design, simulate, and verify analog IP (e.g., references/bandgaps, bias, amplifiers/OTAs, comparators, ADC/DAC front ends, LDOs, clocking/PLL sub-blocks) in planar CMOS nodes.
Account for parasitic effects early (wiring resistance, coupling capacitance, device parasitics), collaborate closely with layout, and drive post-layout (PEX) correlation to meet spec.
Ensure robustness across PVT variations, mismatch (Monte Carlo), supply ripple/noise (PSRR), and temperature range; implement compensation and guard-banding.
Model and mitigate reliability/aging drifts (BTI/HCI) on key parameters (Vth, gm, offset, bias currents) and reflect lifetime targets in design margins.
Define and execute verification plans: corners, Monte Carlo, noise, linearity, transient, stability (phase margin), startup, ESD and latch-up checks in partnership with reliability/ESD teams.
Collaborate with layout on matching strategy (common-centroid/interdigitation, dummies), symmetry, and current density/EM considerations; review DRC/LVS/ERC outcomes affecting electrical intent.
Document assumptions, models, and sign-off criteria; present design reviews and contribute to reusable templates and best practices.
Required Qualifications
5+ years analog circuit design (or equivalent) with tape-out experience in planar CMOS.
Proficiency with SPICE-level simulation flows (AC, DC, noise, transient, other analyses), corner/Monte Carlo, and aging/reliability simulations.
Strong grasp of analog fundamentals: biasing, gain/linearity, noise/offset, PSRR, CMRR, settling, stability/compensation.
Variation-aware design: process/supply/temperature, mismatch, and layout-dependent effects; experience driving PEX correlation.
Working knowledge of layout constraints for matching and reliability (dummies, orientation, guard rings, well ties, current density/EM).

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