Design Verification Engineer (System Verilog / UVM / DDR)

About the Role

We are looking for a highly skilled Design Verification Engineer with strong expertise in System Verilog, UVM methodology, and hands-on experience with DDR protocols. In this role, you will be a key contributor to verifying complex, high-performance digital IP and SoC designs used in next‑generation semiconductor products.

You'll collaborate closely with architects, designers, and fellow verification engineers to ensure robust, high‑quality designs that meet stringent performance and reliability requirements.

Key Responsibilities

• Develop and maintain UVM-based verification environments for digital IP and subsystems
• Create detailed test plans, testbench components, sequences, and functional coverage models
• Execute verification at block, subsystem, and system levels
• Debug design and verification issues using waveform viewers and simulation tools
• Work with design and architecture teams to review specifications and identify corner cases
• Drive improvements in verification methodology, automation, and overall efficiency
• Verify and validate DDR memory controller or PHY interfaces, ensuring compliance with standards
• Perform regressions and ensure high-quality coverage closure

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of hands-on experience in ASIC/FPGA design verification
• Strong skills in SystemVerilog and UVM methodology
• Solid understanding of digital design fundamentals
• Proven experience with DDR protocol verification (DDR3, DDR4, LPDDR4/5, or DDR5)
• Proficiency with simulation, regression, and debugging tools (e.g., VCS, Questa, Incisive)
• Excellent problem‑solving and communication skills