Physical Design Implementation Engineer

Job Description

Your role

As a Physical ASIC Design Implementation Engineer, you'll work on chip design projects from start to finish. You'll handle the entire backend process - taking designs from initial netlist to final GDSII output for both complete chips and individual blocks. You'll work with various technology nodes (from cutting-edge N2 to established 180nm) using Cadence Innovus tools.

In this role you will:

• Build relationships with customers and discuss technical specifications for upcoming projects
• Master and apply the Cadence Innovus Place & Route workflow
• Organize chip designs by dividing them into manageable sections and setting appropriate timing requirements
• Collaborate with the design team throughout the entire development cycle to ensure successful tape-out
• Set up power-efficient designs and troubleshoot timing constraint files

Your profile

• At least 3 years of experience in ASIC physical design
• Knowledge of setting up design workflows for different chip libraries and manufacturing processes
• Understanding of chip layout planning and power distribution for both complete chips and sub-blocks
• Skills in component placement, clock tree design, and routing
• Ability to identify and fix timing problems
• Experience with verification tools for extraction (SPEF/QUANTUS), timing (TEMPUS), and power (VOLTUS)
• Familiarity with physical verification checks (DRC, ERC, LVS, ANT) and design consistency verification

What you'll love about working here

• Flexible work arrangements: Work from home up to 70% of the time, plus our FlexAbroad program lets you work up to 45 days from another country for better work-life balance
• Career development: Access diverse growth programs and career paths designed to help you explore new opportunities
• Inclusive community: Join employee-led networks like OUTfront, Women@Capgemini, or CapAbility that promote diversity, equity, and inclusion in our workplace and beyond