DFT Architect | Semiconductor

Your Role

We are seeking an experienced DFT Architect to join our team in Leuven on a temporary assignment. In this role, you will architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex soft-hard IPs with advanced DFT requirements. You will be responsible for coordinating and negotiating DFT requirements with project teams and customers while implementing innovative testing techniques for complex semiconductor designs.

In this role you will play a key role in:

• Implementing and validating innovative DFT techniques on SOCs and sub-systems, ensuring optimal testability and fault coverage
• Defining timing constraints for DFT test-modes and inserting boundary scan, compression, MBIST-Repair, and OPCG (OCC) for large-scale low-power designs in advanced nodes (7nm and beyond)
• Generating test patterns, debugging and improving fault coverage, supporting debug of post-silicon test patterns, and diagnosing memory and scan issues
• Working closely with the physical design team to address timing violations, signal/power integrity issues, routing congestion, and other physical implementation challenges
• Collaborating with test engineering teams on silicon characterization and validation to ensure seamless transition from design to production
• Defining chip and block-level DFT specifications for projects with hierarchical DFT requirements

Your Profile

• 15+ years of experience in digital ASIC design, with 10+ years of specialized experience in DFT insertion and ATPG
• Experience as a DFT lead defining chip and block-level DFT specifications in projects with hierarchical DFT
• Hands-on experience defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST & repair, OPCG/OCC, ATPG, and fault coverage improvement for large low-power designs in advanced nodes (7nm and beyond)
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL)
• Proficiency with EDA tools such as Genus & Modus (Cadence), Tessent (Siemens), Synopsys toolset and simulation tools
• Strong scripting skills, especially in TCL, and basic fluency with Verilog or VHDL to write code for test logic when needed

What you'll love about working here

• Hybrid working: We encourage flexibility when it comes to when and where work gets done. You'll work with your manager to determine an arrangement that works best for your role and personal circumstances.
• Free access to learning platforms: Enjoy free access to world-class learning assets and curated programs from Harvard Business Review, Coursera, Pluralsight, Udemy, Microsoft, AWS, Google and many more to keep your technical skills at the cutting edge.
• Woman in the Digital Economy: Capgemini supports women at different career stages through various programs, spanning from STEM studies to returning to work or rejoining the company after professional breaks. The global Women in Engineering Network brings together individuals of all genders with a shared dedication to promoting and encouraging more women to pursue careers in engineering.