Senior Engineer Semicon - DV, RTL, PD, DFT

About Capgemini:

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Your role:

DV role:

• Own verification of IP’s and SoC’s in prototype and SoC design environment
• Establish functional and performance benchmarks
• Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms
• IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.

Your profile:

• Sound basics of system Verilog, and good experience in constrained Random and Coverage Driven Verification with UVM/OVM
• Experience in creating any UVC components or sequences is must
• Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.
• Should be comfortable in updating the existing verification environment for feature updates. (bring-up/Architect UVM based Test bench from Scratch is a strong plus)
• EDA simulation/debugging tools agnostic
• Good knowledge of Perl/TCL/Python scripting
• Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.

RTL role:

• Own feasibility studies for defining the system architecture, requirements, and external interfaces
• Develop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out
• Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files
• Work closely with Synthesis, STA, PD, and DFT teams to meet all functional requirements, performance, power, and area goals
• Develop flows and tools as necessary in support of design activities.

Your profile:

• 8+ year experience in VLSI design
• BSC/MSC in Electrical/Computer engineering
• Strong Verilog/System Verilog or VHDL skills
• Experience in defining microarchitecture and design of complex design units
• SoC design experience
• Proficient in advanced design practices (Lint, CDC, and Low Power Design)
• Proficient with the various backend tools (synthesis and STA)
• Familiar with CPU (ARM, RISC-V, or x86) instruction set
• Proficiency using Perl/C/Python scripting and programming
•  Verification methodologies understanding
• Good communication and interpersonal skills.

PD role:

•  Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)
• In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes
• Be part of the overall Low Power solution development and implementation
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level)
• Complete multiple design cycles of high complexity with little supervision.

Your profile:

• 8+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k –1million+ instances in designs
• Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence
• Good knowledge of synthesis flow, insertDFT scan/coverage and optimization
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills
• Proficiency using Perl/TCL/Python scripting and Makefile
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills
• Experience with sign-off tape-out closure work
• Any top level – floor planning, pin assignment – tape out activities is a plus.

DFT role:

• DfT implementation inline with existing test methodology for advance process nodes
• Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST
• Closely work with physical design team to resolve timing constraints/issues
• Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues
• Debug and improve important DfT KPIs: test coverage/pattern efficiency
• Hierarchical retargeting
• Silicon bring-up, diagnosis and support for physical failure analysis.

Your profile:

•  6+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs
• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST
• Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite
• Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus
• Hands-on in Perl/Tcl/Python scripting
•  Excellent analytical, and problem-solving skills.

What Will You Love About Working Here:

• Collaborative and Inclusive Culture: You’ll work alongside passionate engineers striving to provide the best service to our clients and communities with shared interests and identities, in a dynamic environment involving teams spread across different global locations.
• Flexibility and Growth: Enjoy flexible working hours and access to a wide range of professional development opportunities, including training programs, learning platforms and certifications. Whether you're diving into Generative AI, data science, or sustainability, our digital campus supports your learning journey every step of the way;
• Comprehensive Benefits: Benefit from an attractive package including medical services, eye glasses coverage, Benefit online, meal tickets, Employee Assistance Program (covering financial, legal, and emotional matters), and the Employee Share Option Plan.

Capgemini Romania is an equal opportunity employer. We promote equality and dignity in all aspects of recruitment and employment, and all offers of employment and promotions are made on the basis of performance, competence and ability.

About CAPGEMINI:

Capgemini is the business transformation partner for enterprises in the age of AI. We help organizations imagine and build an intelligent, sustainable future, combining AI, technology and human ingenuity to transform how they operate, innovate and grow. With unique end-to-end capabilities spanning strategy, technology, engineering and intelligent operations, we bring together deep industry expertise and market-leading capabilities in AI, cloud and data to turn ambition into measurable business outcomes at scale. Supported by a robust ecosystem of partners and nearly 60 years of expertise, Capgemini is a responsible and diverse global organization of over 410,000 team members in more than 50 countries