As a PnR Design Engineer, you will support the Place & Route workflows for advanced semiconductor designs across 6nm, 3nm, and 2nm technology nodes. You will be responsible for qualifying tools, optimizing flows, enabling new capabilities, and ensuring high‑quality PnR execution in collaboration with CAD, physical design, and verification teams.

In this role, you will:

• Support Place & Route workflows for cutting‑edge nodes such as 6nm, 3nm, and 2nm.
• Qualify new tool versions and deploy updated features into existing flows.
• Apply a strong understanding of low‑power design flows.
• Update and enhance existing workflows with new capabilities based on project requirements.
• Perform CAD PnR flow regressions to ensure flow stability and robustness.
• Work hands‑on with Synopsys Fusion‑Compiler or ICC2 for PnR implementation.
• Use advanced scripting skills in PERL and TCL for debug, automation, and workflow improvements.
• Execute and support synthesis, Place & Route, and STA related activities.
• Utilize physical verification tools for design closure.
• Contribute to PPA improvement, timing correlation, EMIR, and PDV signoff workflows.

Your Profile

• PnR flow qualification, PnR flow support, running multiple PnR blocks to benchmark, PPA push, design correlation with STA, EMIR, PDV signoff flows
• B.Tech / B.E / M.Tech / M.E in Electronics, VLSI, or related fields.