Senior RTL Design Engineer

8+ years of experience in VLSI design.  
BSc/MSc in Electrical or Computer Engineering 
Strong Verilog/SystemVerilog or VHDL skills 
Experience defining microarchitecture and designing complex digital blocks and subsystems 
Strong SoC design experience 
Proficiency in advanced design methodologies including Lint, CDC, RDC, and Low Power Design 
Experience with backend flows, including synthesis and static timing analysis (STA).  
Familiarity with CPU architectures and instruction sets (ARM, RISC-V, or x86).  
Experience with scripting and programming languages such as Python, Perl, or C.  
Understanding of modern verification methodologies and design sign-off flows.  
Experience with Synopsys VC Static CDC/RDC or equivalent verification tools is an advantage. 
Strong analytical, debugging, communication, and collaboration skills. 

Own feasibility studies for defining system architecture, requirements, and external interfaces.  
Develop microarchitecture and RTL design in collaboration with architecture and functional teams, driving projects from specification through tape-out.  
Perform RTL coding, linting, CDC/RDC analysis, and development of timing constraint files (SDC).  
Execute and manage CDC/RDC verification activities at IP, subsystem, and SoC levels to ensure successful design sign-off. 
Review RTL implementations, investigate tool-reported violations, identify root causes, and distinguish genuine design issues from false positives through proper waiver definition. 
Define and maintain CDC/RDC constraints (SDC/SGDC), verification environments, and SoC operating modes. 
Develop, automate, and improve CDC/RDC verification flows based on Synopsys VC Static CDC/RDC tools. 
Define and implement methodologies for automatic generation of IP abstraction models. 
Run and analyze multiple CDC/RDC verification scenarios across different use cases and operating modes. 
Collaborate closely with RTL designers and IP owners to propose robust architectural and RTL solutions for CDC/RDC issues. 
Verify implementation fixes and ensure closure of all CDC/RDC sign-off criteria. 
Work closely with Synthesis, STA, Physical Design, DFT, and Verification teams to achieve functional, timing, power, and area targets.  
Develop design methodologies, automation scripts, and engineering tools to improve productivity and design quality.  

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